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9286bs?rke?06/13 this is a summary document. the complete document is available under nda. for more information, please contact your local atmel sales office. features avr microcontroller core with 1kbyte sram and 24kbyte rf library in firmware (rom) atmel ? ATA5781: 20kbyte of user flash atmel ata5782: 20kbyte of user rom atmel ata5783: no user memory ? rf library in firmware only supported frequency ranges low-band 310mhz to 318mhz, 418mhz to 477mhz high-band 836mhz to 956mhz 315.00mhz/433.92mhz/868.30mhz and 91 5.00mhz with one 24.305mhz crystal low current consumption 9.8ma for rxmode (low-band), 1.2ma for 21ms cycle three-channel polling typical offmode current of 5na (maximum 600na at vs = 3.6v and t = 85c) supports the 0dbm class of arib std-t96 input 1db compression point ?48dbm (full sensitivity level) ?20dbm (active antenna damping) programmable channel frequency with fractional-n pll 93hz resolution for low-band 185hz resolution for high-band fsk deviation 0.375khz to 93khz fsk sensitivity (manchester coded) at 433.92mhz ?108.5dbm at 20kbit/s ? f = 20khz bwif = 165khz ?111dbm at 10kbit/s ? f = 10khz bwif = 165khz ?114dbm at 5kbit/s ? f = 5khz bwif = 165khz ?122.5dbm at 0.75kbit/s ? f = 0.75khz bwif = 25khz ask sensitivity (manchester coded) at 433.92mhz ?110.5dbm at 20kbit/s bwif = 80khz ?125dbm at 0.5kbit/s bwif = 25khz programmable rx-if bandwidth 25khz to 366khz (approximately 10% steps) blocking (bwif = 165khz): 64dbc at freque ncy offset = 1mhz and 48dbc at 225khz high image rejection: 55db at 315mhz/ 433.92mhz and 47db at 868.3mhz/915mhz without calibration atmel ATA5781/ata5782/ata5783 uhf ask/fsk receiver summary datasheet free datasheet http:///
2 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 supported data rate in buffered mode 0.5kbit/s to 80kbit/s (120kbit/s nrz) supports pattern-based wake-up and start of frame identification flexible service configuration concept with on-the-fly (otf) modification (in idlemode) of sram service parameters (data rate, ?) each service consists of one service-specific configuration part three channel-specific configuration parts three service configurations are located in eeprom two service configurations are located in sram and ca n be modified via spi or embedded application software digital rssi with very high relative accuracy of 1db thanks to digitized if processing programmable clock output deriv ed from crystal frequency 1024byte eeprom data memory for receiver configuration spi interface for rx data access and receiver configuration 500kbit spi data rate for short pe riods on spi bus and host controller on demand services (spi or api) wit hout polling or telegram reception integrated temperature sensor self check and calibration with temperature measurement configurable event signal indicates the status of the ic to an external microcontroller automatic low-power channel polling flexible polling configuration concerning timing, order and participating channels fast reaction time power-up (typical 1.5m s, offmode -> rxmode) supports mixed ask/fsk telegrams non-byte aligned data reception software customization antenna diversity with external switch via gpio control antenna diversity with internal spdt switch supply voltage ranges 1.9v to 3.6v and 2.4v to 5.5v temperature range ?40c to +105c esd protection at all pins (4kv hbm, 200v mm, 750v fcdm) small 5 ? 5mm qfn32 package/pitch 0.5mm backward package and pin-to-pin compatibility with atmel ? ata5780n backward rf matching compatibility with atmel ata5780n (rf redesign not needed) suitable for applications governed by en 300 220 and fcc part 15, title 47 free datasheet http:///
3 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 1. general produc t description 1.1 introduction the atmel ? ATA5781/2/3 is a highly in tegrated, low-power uhf ask/fsk rf receiver with an inte grated avr microcontroller. it is package and pin-to-pin compatible with the previous genera tion of rf devices (atmel ata5830n, ata5831/2/3 and atmel ata5780n). the atmel ATA5781/2/3 is partitioned into three sections; an rf front end, a digital baseband and the low-power 8-bit avr microcontroller. the product is designed for the ism frequency bands in the ranges of 310mhz to 318mhz, 418mhz to 477mhz and 836mhz to 956mhz. the external part count is kept to a mini mum due to the very high level of integration in this device. by combining outstanding rf performance with highly sophisticat ed baseband signal processing, robust wireless communication can be easily achieved. the receive path us es a low-if architecture with an integrat ed double quadrature receiver and digitized if processing. this results in high image rejection and exce llent blocking performance. in addition, highly flexible and configurable baseband signal processing allows the receiver to operate in several scanning, wa ke-up and automatic self-polling scenarios. for example, during polling the ic can scan for specific message content (ids) and save valid telegram data in the fifo buffer for later retrieval. the device integrates two rece ive paths that enable a parallel search for two telegrams with different modulations, data rates, wake-up conditions, etc. the atmel ATA5781/2/3 implements a flexible service configur ation concept and supports up to 15 channels. the channels are grouped into five service conf igurations with three channels each. three se rvice configurations ar e located in the eeprom. two service configurations are located in the sram to allow on-the-fly modifications during idlemode via spi commands or application software. the applicat ion software is located in the flash for atmel ATA5781 or in the rom for atmel ata5782. highly configurable and autonomous scanning capability enables flexible polling scenarios with up to 15 channels. the configuration of the receiver is stored in a 1024byte ee prom. the spi interface enables external control and device reconfiguration. in the atmel ATA5781 the internal microcontroller with 20kbyte us er flash can be used to add cu stom extensions to the atmel firmware. the atmel ata5782 provides 20kbyte user rom as a replacement for the 20kbyte flash for high-volume applications. the atmel ata5783 embeds only the firmware rom without user memory. the debugwire and isp interface are available for programming purposes. compatibility to the atmel ata5780n, atmel ata5830n and atmel ata5831/2/3 the atmel ATA5781/2/3 is pin-to-pin compatible with the atme l ata5830n transceiver, the atmel ata5780n receiver and the atmel ata5831/2/3 transceivers. the rx performance of the receivers matches that of the transceivers. table 1-1. program memory comparison of atmel ATA5781/2/3 devices device atmel firmware rom user flash user rom atmel ATA5781 24kbyte 20kbyte - atmel ata5782 24kbyte - 20kbyte atmel ata5783 24kbyte - - free datasheet http:///
4 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 1.2 system overview figure 1-1. circuit overview figure 1-1 shows an overview of the main functional blocks of the atmel ? ATA5781/2/3. extern al control of the atmel ATA5781/2/3 is performed through the spi pins sck, mosi, miso, and nss on port b. the configuration of the atmel ATA5781/2/3 is stored in the eeprom and a large portion of the functionality is defined by the firmware located in the rom and processed by the avr. an spi command can trigger the avr to configure the hardware acco rding to settings that are stored in the eeprom and start up a given system mode (e.g., rx mode, or pollingmode). internal events such as ?start of telegram? or ?fifo empty? are si gnaled to an external microc ontroller on pin 28 (pb6/event). during the start-up of a service, the releva nt part of the eeprom conten t is copied to the sram. this allows faster access by the avr during the subsequent processing st eps and eliminates the need to write to the eeprom during runtime because parameters can be modi fied directly in the sram. as a consequence the user does no t need to observe the eeprom read/write cycle limitations. it is important to note that all pwron and npwron pins (pc1..5, pb4, pb7) are active in offmode. this means that even if the atmel ATA5781/2/3 is in offmode and the dvcc voltage is switched off, the power ma nagement circuitry within the atmel ATA5781/2/3 biases these pins with vs. avr ports can be used as button inputs, external lna supply vo ltage (rx_active), led drivers, event pin, switching control for additional spdt switches, general purpose digital inputs, or wa ke-up inputs, etc. some functi onality of these ports is alre ady implemented in the firmware and can be activated by adequat e eeprom configurations. other functionality is available only through custom software residing in the 20kbyte flash pr ogram memory (atmel ATA5781) or in the 20kbyte user rom program memory (atmel ata5782). rx dsp rf front end rfin data bus src, frc oscillators port b (8) xto xtal pb[7..0] (spi) pc[5..0] port c (6) avr peripherals avr cpu supply reset sram rom flash eeprom free datasheet http:///
5 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 1.3 pinning figure 1-2. pin diagram note: the exposed die pad is connected to the internal die. table 1-2. pin description pin no. pin name type description 1 rfin_lb analog lna input for low-band frequency range (< 500mhz) 2 rfin_hb analog lna input for high-band frequency range (> 500mhz) 3 spdt_rx analog rx switch output (damped signal output) 4 spdt_ant analog antenna input (rxmode) of the spdt switch 5, 7 nc - open in application 6 spdt_rx2 analog rx switch output 2 (damped signal output) 8 vs_spdt analog spdt supply 3v application supply voltage input 9 test_en ? test enable, connected to gnd in application 10 xtal1 analog crystal oscillator pin 1 (input) 11 xtal2 analog crystal oscillator pin 2 (output) 12 avcc analog rf front end supply regulator output 13 vs analog main supply voltage input 14 pc0 digital main alternate : avr port c0 : pcint8 / nreset / debugwire rfin_lb rfin_hb agnd pb7 pb6 pb5 pb4 pb3 pc2 pc1 pc0 vs avcc xtal2 xtal1 test_en spdt_rx spdt_ant nc spdt_rx2 nc vs_spdt pb2 32 1 2 exposed die pad 3 4 5 6 7 8 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 9 10111213141516 pb1 pb0 dgnd dvcc pc5 pc4 pc3 atmel ATA5781 ata5782 ata5783 atest_io2 atest_io1 free datasheet http:///
6 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 15 pc1 digital main alternate : avr port c1 : npwron1 / pcint9 / ext_clk 16 pc2 digital main alternate : avr port c2 : npwron2 / pcint10 / trpa 17 pc3 digital main alternate : avr port c3 : npwron3 / pcint11 / tmdo / txd 18 pc4 digital main alternate : avr port c4 : npwron4 / pcint12 / int0 / rxd 19 pc5 digital main alternate : avr port c5 : npwron5 / pcint13 / trpb / tmdo_clk 20 dvcc ? digital supply voltage regulator output 21 dgnd ? digital ground 22 pb0 digital main alternate : avr port b0 : pcint0 / clk_out 23 pb1 digital main alternate : avr port b1 : pcint1 / sck 24 pb2 digital main alternate : avr port b2 : pcint2 / mosi (spi master out slave in) 25 pb3 digital main alternate : avr port b3 : pcint3 / miso (spi master in slave out) 26 pb4 digital main alternate : avr port b4 : pwron / pcint4 / led1 (strong high side driver) 27 pb5 digital main alternate : avr port b5 : pcint5 / int1 / nss 28 pb6 digital main alternate : avr port b6 : pcint6 / event (f irmware controlled external microcontroller event flag) 29 pb7 digital main alternate : avr port b7 : npwron6/ pcint7/ rx_active (strong high side driver) / led0 (strong low side driver) 30 agnd ? analog ground 31 atest_io2 ? rf front end test i/o 2 connected to gnd in application 32 atest_io1 ? rf front end test i/o 1 connected to gnd in application gnd ? ground/backplane on exposed die pad table 1-2. pin description (continued) pin no. pin name type description free datasheet http:///
7 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 1.4 typical applications the receiver is designed to be used in the following application areas: remote keyless entry system (rke) passive entry go system (peg) tire pressure monitoring system (tpm, tpms) remote start system (rs) remote control systems, e.g., garage door openers smart rf applications telemetering systems 1.4.1 typical 5v application circ uit with external microcontroller figure 1-3. typical 5v application circuit with external microcontroller figure 1-3 shows a typical vehicle side application circuit with an external host microcontroller running from a 5v voltage regulator. the pin pb4 (pwron) is direct ly connected to vs and the atmel ATA5781/2/3 enters the idlemode after power-on. in this configuration the atmel ATA5781/2/3 can work aut onomously and the c stays powered down to keep current consumption low while remaining sensitive to rf telegrams. to achieve a low current in idlemode the atmel ATA5781/2/3 can be c onfigured in the eeprom to wo rk with the rc oscillator. the atmel ATA5781/2/3 can also be configured for autonomous mu lti-channel and multi-application pollingmode. the external c is notified by an event on pin 28 (event) if an appropriate rf message is received. until th is event, the atmel ATA5781/2/3 periodically switches to rxmode , checks the different servic es and channels co nfigured in the eepr om, and returns to power-down while the external host microcontroller is still in de ep sleep mode to keep average current low. once a valid rf message is detected, it can be buffered insi de of the atmel ATA5781/2/3 to enable a c wake-up and retrieval of buffered data. rf_in is matched to spdt_rx by absorbing the parasitics of the spdt switch into the matching network, hence the spdt_ant is a 50 ? rx port. rfin_lb irq nss miso mosi sck vdd clk_in atest _io1 atest _io2 test _en rfin_hb agnd pb7 pb6 pb5 pb4 pb3 pc2 pc1 pc0 vs avcc xtal2 xtal1 spdt_rx spdt_ant nc spdt_rx2 nc vs_spdt pb2 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 910111213 1415 16 pb1 pb0 dgnd dvcc pc5 pc4 pc3 vs = 5v vs microcontroller atmel ATA5781 ata5782 ata5783 saw free datasheet http:///
8 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 the impedance of the saw filter is transformed with lc matching circuits to the spdt_ant port and also to the antenna. an external crystal, together with the fractional-n pll within the atmel ? ATA5781/2/3 is used to fix the rx frequency. accurate load capacitors for this crystal are integrated, to reduce system part count and cost. only three supply blocking capacitors are needed to decouple the different supply voltages avcc, dvcc and vs of the atmel at a5781/2/3. the exposed die pad is the rf and analog ground of the atmel ATA5781/ 2/3. it is directly connected to agnd vi a a fused lead. for applications operating in the 868.3mhz or 915mhz frequency bands, a high-band rf inpu t is supplied, rfin_hb, and must be used instead of rfin_lb. the atmel ATA5781/2/3 is controlled using specific sp i commands via the spi interf ace and an internal eeprom for application specific configuratio n. this application is compatible to the atme l ata5831/2/3, therefore, the same application board can be used for both devices, just the population of the tx path is not required for the atmel ATA5781/2/3.. 2. system functional description 2.1 overview 2.1.1 service-based concept the atmel ? ATA5781/2/3 is a highly configurable uhf receiver. the co nfiguration is stored in an internal 1024-byte eeprom. the master system control is performed by firmware. genera l chip-wide settings are loaded from the eeprom to hardware registers during system initialization. duri ng start-up of a receive mode the specific settings are loaded from the eeprom or sram to the current service in the sram and fr om there to the corresponding hardware registers. a complete configuration set of the receiver is called ?servi ce? and includes rf settings, demodulation settings, and telegram handling information. each service contains three ch annels which differ in the rf receive frequencies. the atmel ATA5781/2/3 supports five servic es which can be configured in various ways to meet customer requirements. three service configurations are located in th e eeprom space. they are fixed configur ations which should not be changed during runtime. two service configurations are located in the sram space and can be modified by user sw in a flash application or by an spi command during idlemode. a service consists of one service-specific configuration part three channel-specific configuration parts further configurations for pollingmode and rssi are available and can be modified in idlemode via an spi command and/or user sw. figure 2-1 on page 9 gives an overview on the service based-concept. free datasheet http:///
9 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 figure 2-1. service-based concept overview 2.1.2 supported telegrams the atmel ? ATA5781/2/3 supports the reception of a wide variety of telegrams and protocol s. generally no special structure is required from a telegram to be received by the atmel ata 5781/2/3. however, designated har dware and software features are built in for the blocks that are depicted in figure 2-2 . using this structure or parts of it can increase the sensitivity and robustness of the broadcast. figure 2-2. telegram structure desync: the de-synchronization is usually a coding violation with a lengt h of several symbols that shoul d provoke a defined restart of the receiver. the use of a de-synchronization leads to more determi nistic receiver behavior, reducing the required preamble length. this can be favorable in timing-critic al and energy-critical applications. preamble: the preamble is a pattern that is sent before the actual data payload to synchronize the receiver and provide the starting poin t of the payload. a very regular patter n (e.g., 1-0-1-0...) is recommended for synchronization (?wake-up pattern, wup?, sometimes also called ?pre-burst?) while a unique, well-defined patt ern of up to 32 symbols is required to mark the start of the data payload (?start frame identifier, sfid? or ?start bit?). in polling scenarios the wup can be tens or hundreds of ms long. eeprom system initialization channel 0 channel 1 channel 2 eeprom polling configuration eeppollloopconf service 0 eepservices [0] channel 0 channel 1 channel 2 service 1 eepservices [1] channel 0 channel 1 channel 2 service 2 eepservices [2] channel atmel ATA5781/2/3 hardware service s currentservice sram spi channel 0 channel 1 channel 2 sram polling configuration pollconfig service 3 sramservices [0] channel 0 channel 1 channel 2 service 4 sramservices [1] rssi threshold configuration for each channel rssithreshold [][] desync preamble data payload checksum stop sequence free datasheet http:///
10 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 data payload: the data payload contains the actual informa tion content of the telegram . it can be nrz or manchester-coded. the length of the payload is application dependen t, typically 1..64 bytes. checksum: a checksum can be calculated acro ss the data payload to ve rify that the data have been received correctly. a typical example is an 8-bit crc checksum. data bits at the beginning of the payload can be excluded from the crc calculation. stop sequence: the stop sequence is a short data pattern (typically 2 to 6 symbo ls) to mark the end of the telegram. a coding violation can be used to prevent additional (non-determ inistic) data from being received. 2.2 operating modes overview this section gives an overview of the operating modes supported by the atmel ? ATA5781/2/3 as shown in figure 2-3 . figure 2-3. operating modes overview after connecting the supply voltage to the vs pin, the atmel ata 5781/2/3 always starts in offmod e. all internal circuits are disconnected from the power supply. theref ore, no spi communication is supported. the atmel ATA5781/2/3 can be woken up by activating the pwron pin or one of the npwronx pins. this triggers the power-on sequence. after the system initialization the atmel ATA5781/2/3 reaches the idlemode. the idlemode is the basic system mode suppor ting spi communication and transitions to all other operating modes. there are two options of the idlemode requiring configuration in the eeprom settings: idlemode(rc) with low power consumption using the fast rc (frc) oscillator for processing idlemode(xto) with active crystal oscillator for high accuracy clock output or timing measurements the receive mode (rxmode) provides data reception on the select ed service/channel configuration. the precondition for data reception is a valid preamble. the receiver continuously scans for a valid telegram and receives the data if all pre-configured checks are successful. the rxmode is usually enabled by the spi command ?set system mode?, or directly after power-on, when selected in the eeprom setting. the pure receive mode (purerxmode) is a unique receive mode only available as transparent mode. there is no precondition for data reception necessary. it must be enabled in the eepr om settings and is activated by a special use of pin 18. in pollingmode the receiver is activated for a short period of ti me to check for a valid telegram on the selected service/chann el configurations. the receiver is deactivated if no valid telegr am is found and a sleep period with very low power consumption elapses. this process is repeated periodically in accordance with the polling configuration. pollingmode init done power-on wdr idlemode rxmode system initialization offmode tcmode extr purerxmode invalid wake-up system error loop init fails free datasheet http:///
11 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 the initial settings are stored in the eeprom and copied during firmware in itialization to t he sram. this allo ws modification o f the pollingmode timing and service/ channel configuration during idlemode. the tune and check mode (tcmode) offers calibration and self-c hecking functionality for the vc o and frc oscillators as well as for temperature measurement, and polling cycle accuracy. this mode is activated via the spi command ?calibrate and check?. when selected in the eeprom settings, tune and chec k tasks are also used during system initialization after power- on. furthermore, they can also be ac tivated periodically during pollingmode. table 2-1 shows the relations between the operating modes and thei r corresponding power supplies, clock sources, and sleep mode settings. notes: 1. during idlemode(rc) and idlemode(xto) the avr mi crocontroller enters sleep mode to reduce current con- sumption. the sleep mode of the microcontroller sect ion can be defined in the eeprom. the power-down mode is recommended for keeping current consumption low. table 2-1. operating modes versus power supplies and oscillators operation mode avr sleep mode dvcc avcc xto src frc offmode - off off off off off idlemode(rc) active mode power-down (1) on off off off off on on on off idlemode(xto) active mode power-down (1) on on on on on on off off rxmode active mode on on on off pollingmode(rc) - active period - sleep period active mode power-down (1) on off on off on on on off pollingmode(xto) - active period - sleep period active mode power-down (1) on on on on on on off off free datasheet http:///
12 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 3. hardware description 3.1 overview the atmel ? ATA5781/2/3 consists of an analog front end, digital signal processing blocks (dsp), an 8-bit avr sub-system and various supply modules such as oscillators and power regula tors. a hardware block diagram of the atmel at a5781/2/3 is shown in figure 3-1 . figure 3-1. block diagram together with the fractional-n pll, the cr ystal oscillator (xto) generates the local oscillator (lo) signal for the mixer in rxmode. the rf signal comes either from the low-band inpu t (rfin_lb) or from the high-band input (rfin_hb) and is amplified by the low-noise amplifier (lna) and down-converted by the mixer to the intermediate frequency (if) using the lo signal. a 10db if amplifier with low-pass f ilter characteristic is used to achieve enhanced system sensitivity without affectin g blocking performance. after the mixer, the if signal is sampled using a high-resolution analog-to-digital converter (adc). within the rx digital signal processing (rx dsp) the received si gnal from the adc is filtered by a digital channel filter and demodulated. two data receive paths, path a and path b, are included in the rx dsp afte r the digital channel filter. in addition, the receive path can be configured to provide the di gital output of an internal temperature sensor (temp( ? )). lna, mixer if amp rx dsp a d rf front end rfin_lb rfin_hb spdt_rx spdt_ant spdt_rx2 vs_spdt frequency synthesizer te m p ( ? ) xto xtal1 xtal2 pb[7:0] data bus pc[5:0] irq crc avcc dvcc vs rom 24kb avr cpu flash 20kb (1) eeprom 1152b sram 1kbyte 16 bit sync timer watchdog timer front-end registers src, frc oscillators clock management debug wire nvm controller port b (8) spi port c (6) 16 bit async timers 2x fractional n-pll supplies and reset sequencer state machine voltage monitor spdt damping 8 bit async timers 2x support fifo data fifo (1) 20kbyte flash for atmel ata5782, 20kbyte user rom for atmel ata5783, no user memory for atmel ATA5781 avr sub- system free datasheet http:///
13 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 with the single pole double throw (spdt) switch the rf signal from the antenna is switched to rfin in rxmode. the system is controlled by an avr cpu with 24kb firmware rom and 20kb user flas h for the atmel ? ATA5781, or with 20kb user rom for the atmel ata5782. 1024-by te eeprom, 1024-byte sram, and other peripherals are supporting the receiver handling. two gpio ports, pb[7:0] and pc[5:0], are available fo r external digital connections, for example, as an alternate function the spi interface is connected to port b. t he atmel ATA5781/2/3 is controlled by the eeprom configuration and spi commands and the functional behavior is mainly determined by firmw are in the rom. much of the configuration can be modified by the eeprom settings. the firmware running on the avr gi ves access to the hardware functionality of the atmel ATA5781/2/3. extensions to this firmware can be added in th e 20kb of flash memory for the atmel ATA5781. the rx dsp registers are addressed directly and accessible from the avr. a se t of sequencer state machines is included to perform rx path operations (such as enable, disable, receive) which require a defined timing parallel to the avr program execution. the power management contains low-dropout (ldo) regulators and reset circuits for the supply voltages vs, avcc, and dvcc of the atmel ATA5781/2/3. in offmode all the supply voltages avcc and dvcc are s witched off to achieve very low current consumption. the atmel ata57 81/2/3 can be powered up by activating the pwron pin or one of the npwron[6:1] pins because they are still active in offm ode. the avcc domain can be switched on and off independently from dvcc. the atmel ATA5781/2/3 includes two idle modes. in idlemode(rc) only the dvcc voltage regulator, the frc and src oscillators are active and the avr uses a power-down mode to achieve low current consumption. the same power-down mode can be used during the inactive phases of the pollingmode. in idlemo de(xto) the avcc voltage domain as well as the xto are additionally activated. an integrated watchdog timer is available to restart the atmel at a5781/2/3 when it is not served within the configured time-out period. 3.2 receive path 3.2.1 overview the receive path consists of a low-noise amp lifier (lna), mixer, if amplifier, analog- to-digital converter (adc), and an rx dig ital signal processor (rx dsp). the fractional-n pll and the xto deliver the local oscillator frequency in rxmode. the receive path is controlled by the rf front-end registers. two separate lna inputs, one for low-band and one for high-band, are provided to obtain optimum performance matching for each frequency range and to allow multi-band applications. a radio frequency (rf) level detec tor at the lna output and a switchable damping included into the single-pole double-trough (spd t) switch is used in the presence of large blockers to achieve enhanced system blocking performance. the mixer converts the received rf signal to a low inte rmediate frequency (if) of ab out 250khz. a double-quadrature architecture is used for the mixer to achieve high image rejecti on. additionally, the third-order suppression of the local osci llator (lo) harmonics makes receiving without a front-end saw filt er less critical, such as in a car key fob application. an if amplifier provides additional gain and improves the receiver sensitivity by 2-3d b. because of built-in filter function, t he in- band compression is degraded by 10db, while the out-of-band compression remains unchanged. the adc converts the if signal into the di gital domain. due to the high effective reso lution of the adc, the channel filter and received signal strength indicato r (rssi) can be realized in the digital signal domain. therefore, no ana log gain control (agc) potentially leading to critical timing issues or analog filteri ng is required in front of the adc. this leads to a receiver fro nt end with excellent blocking performance up to the 1db compression poin t of the lna and mixer, and a steep digital channel filter ca n be used. the rx dsp performs the channel filtering an d converts the digital output signal of the adc to the baseband for demodulation. due to the digital realization of these functions the rx dsp ca n be adapted to the needs of many different applications. channe l bandwidth, data rate, modulati on type, wake-up criteria, signal checks, clo ck recovery, and many other properties are configurable. the rssi value is realized completely in the digital signal domain, enabling very high relative and absolute accuracy that is only deteriorated by the gain errors of the lna, mixer, and adc. two independent receive paths a and b are integrated in the rx dsp after the channel filter and a llow the use of different data rates, modulation types, and protocols without the need to power up the receive path more than once to decide which signal should be received. this results in a reduced polling current in several applications. the integration of re mote keyless entry (rke), passive entry and go (peg) and tire-pressu re monitoring systems (tpm) into one module is simplified because completely different protocols can be supported and a low polling current is achieved. it is even possible to configure different receive rf bands for differ ent applications by using the two lna inputs. for example, a tpm receiver can be realized at 433.92mhz while a peg syst em uses the 868mhz is m band with multi-channel communication. free datasheet http:///
14 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 3.2.2 rx digital signal processing (rx dsp) the rx digital signal processing (dsp) block performs the digital filtering, decoding, checking, and byte-wise buffering of the rx samples that are derived from the adc as shown in figure 3-2 . the rx dsp provides the following outputs: raw demodulated data at the trpa/b pins decoded data at the tmdo and tmdo_clk pins buffered data bytes toward the data fifo and id check block auxiliary information about the signal such as the received signal strength indication (rss i) and the frequency offset of the received signal from the se lected center frequency (rxfoa/b) figure 3-2. rx dsp overview the channel filter determines the receiver ban dwidth. its output is used for both rece iving paths a and b, making it necessary to configure the filter to match both paths. the receiving paths a and b are id entical and consist of an ask/fsk demodulator with attached signal checks, a frame synchronizer which supports pa ttern-based searches for the telegram start and a 1-byte hardware buffer with integrated crc checker for the received data. depending on the signal checks, one path is selected which writes the received data to the data fifo and optionally to the id check block. the rssi values are determined by the demodulator and writte n via the rssi buffer to the support fifo where the latest 16 values are stored for further processing. tmdo_a tmdo_clk_a tmdo_b tmdo_clk_b rxfoa trpa rxfob trpb rssi demod & check path a data byte path b rx buffer a rx buffer b rssi buffer frame sync a frame sync b = = id check = support fifo data fifo data byte channel filter adc data free datasheet http:///
15 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 3.3 avr controller 3.3.1 avr controller sub-system the avr controller sub-system consists of the avr cpu core, its program memory, and a data bus with data memory and peripheral blocks attached. the receive path also has its user in terfaces connected to the data bus. 3.3.2 cpu core the main function of the cpu core is to ensure correct program execution. for this reason, the cpu core must be able to access memories, perform calculations, control peripherals, and handle interrupts. figure 3-3. architectural overview in order to maximize performance and parallelism, the avr uses a harvard architecture?wit h separate memories and buses for program and data. instructions in the program memory are ex ecuted with single-level pipelining. while one instruction is being executed, the next instruct ion is prefetched from the progr am memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory and rom. the fast-access register file contains 32 ? 8-bit general purpose working registers wi th a single clock cycle access time. this allows a single-cycle arithmetic and logic unit (alu) operation. in a typical alu oper ation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file?in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register poin ters for data space addressing, enabling efficient address calculations. one of thes e address pointers can also be used as an address pointer for lookup tables in the flash program memory. referred to as ?x,? ?y,? and ?z? regi sters, these higher 16-bit function registers are described later in this section. status and control interrupt unit spi unit 32 x 8 general purpose registers alu data bus 8-bit data sram watchdog timer instruction register instruction decoder clock management eeprom portn control lines direct addressing indirect addressing i/o module n program counter rom flash program memory i/o module 1 free datasheet http:///
16 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 the alu supports arithmetic and logic operat ions between registers or between a cons tant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect informatio n about the result of the operation. the program flow is provided by conditional and unconditional ju mp and call instructions which are able to directly address the entire address space. most avr instructio ns have a single 16-bit word format. ever y program memory address contains a 16- or 32-bit instruction. the program memory space is divided in two sections, the boot program section and the application program section. both sections have dedicated lock bits for write and read/write protec tion. the store program memory (spm) instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address of th e program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram ?the stack size is thus only limited by the total sram size and the usage of the sram. all user programs must initialize t he stack pointer (sp) in the reset routine before subroutines or interrupts are execut ed. the sp is read/write accessible in the i/o space. the data sram can easily be acce ssed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its contro l registers in the i/o space with an additional global interrupt enable bit in the st atus register. all interrupts have a separate inte rrupt vector in the interrupt vector tabl e. the interrupts have priority in accord ance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space lo cations following those of the register file, 0x20 - 0x5f. in addition, the circuit has extended i/o space from 0x60 - 0x1ff and sram where only the st/sts/std and ld/lds/ldd instructions can be used. free datasheet http:///
17 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 3.4 power management the ic has four power domains: 1. vs ? unregulated battery voltage input 2. dvcc ? internally regulated digital supply voltage. typical value is 1.35v. 3. avcc ? internally regulated rf front end and xto supply. typical value is 1.85v. 4. vs_spdt ? this is used to achieve full pcb and rf application compatibility with atmel ? ata5831/2/3, in atmel ATA5781/2/3 this supply is always switched off and connected externally to the battery in 3v applications: the atmel ATA5781/2/3 can be operated from v s = 1.9v to 3.6v (3v applications) and from v s = 2.4v to 5.5v (5v application). figure 3-4. power supply management power management (common reference, voltage monitor) avcc regulator port b spi port c 220nf 68nf 22nf 2.2f avcc vs vs xtal1 ... level shifter rfin_lb rfin_hb spdt_rx spdt_ant xtal2 vs_spdt (only 3v operation) ... ... data bus pb7 pb4 pc1 pc5 dvcc regulator avr cpu, avr peripherals, memories, rxdsp and frc/src rf front end and xto dvcc spdt_rx2 free datasheet http:///
18 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 5. package information 4. ordering information extended type number package remarks ATA5781-pnqw qfn32 5mm x 5mm, 6k tape and reel, pb-free ata5782- nnn -pnqw qfn32 5mm x 5mm, 6k tape and reel, pb-free, nnn = customer rom identifier ata5783-pnqw qfn32 5mm x 5mm, 6k tape and reel, pb-free package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5124.01-4 3 09/07/11 package: vqfn_5x5_32l exposed pad 3.6x3.6 common dimensions (unit of measure = mm) min nom note max symbol standard singulation process dimensions in mm specifications according to din technical drawings 0.02 0.05 0.0 a1 55.1 4.9 e 0.23 0.3 0.16 b 0.5 bsc e 0.4 0.5 0.3 l 3.6 3.75 3.45 e2 3.6 3.75 3.45 d2 55.1 4.9 d 0.2 0.25 0.15 a3 0.9 1 0.8 a top view d 32 1 8 pin 1 id e a3 a a1 b l z 10:1 side view bottom view d2 e 32 25 9 17 24 16 8 1 e2 z free datasheet http:///
19 atmel ATA5781 [sum mary datasheet] 9286bs?rke?06/13 6. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 9286bs-rke-06/13 ?? features on pages 1 to 2 updated free datasheet http:///
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